Shared Memory Architectures: A Comprehensive Guide for Computer Architecture Students

Question 1

In shared memory architectures, how do sequential consistency and weak consistency differ?

Accepted Answer

Sequential consistency ensures writes to shared memory are visible to all processors in the same order, while weak consistency allows for reordering.

Answer

Weak consistency is stricter than sequential consistency, enforcing a specific write order.

Answer

Performance is better with sequential consistency than with weak consistency.

Answer

Implementing sequential consistency is more straightforward than implementing weak consistency.

Question 2

In a shared memory architecture, which component is primarily responsible for maintaining cache coherence?

Accepted Answer

Cache controller

Answer

Operating system

Answer

Memory controller

Answer

Processor

Question 3

Which memory consistency model guarantees that all processors observe writes to shared memory in the same order?

Accepted Answer

Sequential consistency

Answer

Release consistency

Answer

Weak consistency

Answer

Total store ordering

Question 4

Which of the following is NOT a characteristic of a symmetric multiprocessing (SMP) architecture?

Accepted Answer

Processors are loosely coupled and have separate caches

Answer

Multiple processors share a common physical memory

Answer

All processors have equal access to memory and I/O devices

Answer

A central kernel is responsible for scheduling and synchronization

Question 5

Which of the following is a defining characteristic of symmetric multiprocessing (SMP) architectures?

Accepted Answer

Multiple processors sharing memory

Answer

Single processor with multiple cores

Answer

Hierarchical memory organization

Answer

Asymmetric cache access latency

Question 6

What is the primary purpose of a cache coherence protocol in a shared memory system?

Accepted Answer

To ensure data consistency among multiple cores

Answer

To reduce memory access latency

Answer

To improve processor utilization

Answer

To detect and correct memory errors

Question 7

Which of the following is NOT a recognized memory consistency model?

Accepted Answer

Eventual consistency

Answer

Sequential consistency

Answer

Weak consistency

Answer

Total store order

Question 8

What is the primary distinction between a snooping cache coherence protocol and a directory-based protocol?

Accepted Answer

Broadcast vs. point-to-point communication

Answer

Centralized vs. distributed control

Answer

Read vs. write operations

Answer

Cache line size

Question 9

What is the primary purpose of a memory fence instruction?

Accepted Answer

To enforce ordering of memory operations

Answer

To invalidate stale cache lines

Answer

To synchronize threads

Answer

To reduce memory bandwidth

Question 10

In a shared memory architecture, which mechanism ensures that all processors have a consistent view of the shared memory?

Accepted Answer

Cache coherence protocol

Answer

Virtual memory

Answer

Memory management unit (MMU)

Answer

Paging

Question 11

In a symmetric multiprocessing (SMP) system, which of the following statements is true?

Accepted Answer

All processors have equal access to shared memory.

Answer

One processor is designated as the master processor.

Answer

Processors are organized in a hierarchical structure.

Answer

Processors communicate through a shared bus.

Question 12

Which of the following memory consistency models provides the strongest consistency among processors?

Accepted Answer

Sequential consistency

Answer

Relaxed consistency

Answer

Weak consistency

Answer

Eventual consistency

Question 13

In a shared memory architecture, what is the primary responsibility of a memory controller?

Accepted Answer

Manage access to shared memory

Answer

Maintain cache coherence

Answer

Enforce memory consistency

Answer

Translate virtual addresses to physical addresses

Question 14

Which key feature distinguishes a symmetric multiprocessing (SMP) architecture?

Accepted Answer

Shared memory accessible by all processors

Answer

Private memory for each processor

Answer

Inter-processor communication via message passing

Answer

Crossbar switch for processor interconnection

Question 15

Which cache coherence protocol guarantees the consistency of shared variables across cache copies?

Accepted Answer

MESI protocol

Answer

MSI protocol

Answer

MOSI protocol

Answer

No cache coherence protocol can guarantee absolute consistency

Question 16

Which technique is commonly employed to minimize the overhead associated with snoopy-based cache coherence protocols?

Accepted Answer

Snoop filtering

Answer

Directory-based coherence

Answer

Write-invalidate protocol

Answer

Limited-broadcast protocol

Question 17

In a multi-core processor with a shared L3 cache, what is a potential challenge that may arise?

Accepted Answer

Cache contention

Answer

Data inconsistency

Answer

Processor synchronization

Answer

Increased memory latency

Question 18

In a task-based programming model, which component manages efficient task scheduling and load balancing?

Accepted Answer

Scheduler

Answer

Compiler

Answer

Operating system

Answer

None of the mentioned

Question 19

In a multithreaded environment, which memory consistency model guarantees that memory operations are executed in the exact order specified by the program?

Accepted Answer

Sequential Consistency

Answer

Processor Consistency

Answer

Weak Consistency

Answer

Relaxed Consistency

Question 20

What is the primary objective of a memory consistency model?

Accepted Answer

Ensuring a consistent view of memory across all processors

Answer

Preventing data corruption in shared memory

Answer

Optimizing memory access patterns

Answer

Supporting virtual memory implementation

Question 21

What is the purpose of utilizing a snoop filter in a shared memory system?

Accepted Answer

Reducing the frequency of snoop operations performed by each processor

Answer

Preventing incorrect data from being written to memory

Answer

Ensuring that all processors receive a copy of every memory write

Answer

Detecting and handling memory errors

Question 22

Which memory consistency model provides the highest level of memory consistency guarantees?

Accepted Answer

Sequential Consistency

Answer

Processor Consistency

Answer

Weak Consistency

Answer

Release Consistency

Question 23

Which of the following is NOT a benefit of shared memory architectures?

Accepted Answer

Eliminated security concerns

Answer

Improved performance for parallel applications

Answer

Simplified programming model

Answer

Reduced memory overhead

Question 24

In a symmetric multiprocessing (SMP) architecture, all processors share:

Accepted Answer

A common memory

Answer

Their own private memory

Answer

Specific tasks based on their capabilities

Answer

An operating system that manages memory access

Question 25

Which cache coherence protocol ensures that all copies of a shared data item in the cache are always consistent with the main memory?

Accepted Answer

MOESI protocol

Answer

MSI protocol

Answer

MESI protocol

Answer

Dragon protocol

Question 26

In a multiprocessor system with a shared memory, what is the primary purpose of a lock?

Accepted Answer

To prevent multiple processors from accessing the same shared data simultaneously

Answer

To optimize memory access speed

Answer

To ensure cache coherence

Answer

To manage virtual memory

Question 27

In a shared memory architecture, what is the primary cause of write conflicts?

Accepted Answer

Multiple processors writing to the same memory location

Answer

Cache incoherence

Answer

Memory bus contention

Answer

Deadlocks

Question 28

Which of the following is NOT a technique used to improve cache coherence in shared memory architectures?

Accepted Answer

Virtual memory paging

Answer

Write-back caching

Answer

Invalidate-on-write protocol

Answer

Snooping-based protocols

Question 29

What is the main advantage of using a distributed shared memory (DSM) system?

Accepted Answer

Increased scalability

Answer

Improved performance

Answer

Reduced memory overhead

Answer

Simplified programming

Question 30

Which memory consistency model guarantees that all threads witness write operations to shared memory in a uniform sequence?

Accepted Answer

Sequential consistency

Answer

Weak consistency

Answer

Processor consistency

Answer

Eventual consistency

Question 31

Which of the following challenges is associated with shared memory architectures?

Accepted Answer

Increased complexity in managing memory access conflicts

Answer

Reduced fault tolerance due to a single point of failure

Answer

Higher hardware costs compared to distributed memory architectures

Question 32

In a shared memory architecture, which technology is commonly used to interconnect processors?

Accepted Answer

Crossbar switch

Answer

Fibre channel

Answer

InfiniBand

Answer

Network interface card

Question 33

Which aspect is central to a write-invalidate cache coherence protocol?

Accepted Answer

When a processor writes to a cache line, copies in other caches are invalidated

Answer

When a processor reads a cache line, the latest copy is retrieved from main memory

Answer

When a processor writes to a cache line, it sends a copy to all other caches

Question 34

Which drawback is associated with using a write-back protocol in a shared memory architecture?

Accepted Answer

Increased risk of data loss in case of system crashes

Answer

Increased hardware complexity

Answer

Reduced performance due to frequent writebacks

Question 35

Which technique is employed to improve the performance of shared memory architectures?

Accepted Answer

Prefetching

Answer

Virtualization

Answer

Data compression

Answer

Load balancing

Question 36

In a symmetric multiprocessing (SMP) architecture, what is responsible for ensuring data consistency across caches?

Accepted Answer

Cache coherency protocol

Answer

Compiler-enforced memory access rules

Answer

Centralized hardware lock manager

Answer

Operating system resource manager

Question 37

Which memory consistency model guarantees that all processors will observe writes to shared memory in the same order?

Accepted Answer

Sequential consistency

Answer

Weak consistency

Answer

Total store order

Answer

Eventual consistency

Question 38

In a shared memory architecture, which factors can influence cache miss rates?

Accepted Answer

Cache associativity, cache size, and memory access patterns

Answer

Processor clock speed

Answer

Operating system scheduling policies

Question 39

Which hardware component typically serves as the main memory in shared memory architectures?

Accepted Answer

DRAM (Dynamic Random Access Memory)

Answer

EEPROM (Electrically Erasable Programmable Read-Only Memory)

Answer

SRAM (Static Random Access Memory)

Answer

ROM (Read-Only Memory)

Question 40

What is a fundamental difference between shared memory and distributed memory architectures?

Accepted Answer

Shared memory has a single, globally accessible memory space, while distributed memory does not.

Answer

Shared memory is typically used in larger systems, while distributed memory is used in smaller systems.

Answer

Shared memory has lower latency in memory access compared to distributed memory.

Question 41

The 'sequentially consistent' memory consistency model ensures that:

Accepted Answer

All memory operations appear to execute in the order specified by the program, as if they were executed on a single processor.

Answer

Updates to shared memory variables become immediately visible to all processors, regardless of the order of operations.

Answer

Processor instructions are reordered to optimize performance, potentially leading to unexpected results.

Question 42

In the context of shared memory architectures, what is the primary purpose of a directory-based cache coherence protocol?

Accepted Answer

To maintain a central directory that tracks the location of shared data in each processor's cache, enabling efficient cache coherence maintenance.

Answer

To invalidate cache lines that contain outdated data, ensuring data consistency.

Answer

To lock memory regions that are being written to by multiple processors, preventing conflicts.

Question 43

In a Symmetric Multiprocessing (SMP) system, what do all processors have direct access to?

Accepted Answer

Shared memory space

Answer

Virtual memory space

Answer

Separate dedicated memory

Answer

Exclusive local cache

Question 44

Which cache coherence protocol ensures that all processors have a consistent view of shared data?

Accepted Answer

MESI (Modified, Exclusive, Shared, Invalid)

Answer

Write-Broadcast Protocol

Answer

Snooping Protocol

Answer

Write-Invalidate Protocol

Question 45

What is the primary function of a memory consistency model?

Accepted Answer

Defining the order in which memory operations become visible to processors

Answer

Ensuring data integrity during data transfer

Answer

Managing allocation of memory space to processes

Question 46

Which memory consistency model allows the most flexibility in ordering of memory operations, potentially leading to performance benefits but also posing challenges for program reasoning?

Accepted Answer

Relaxed Consistency

Answer

Cache Coherence

Answer

Sequential Consistency

Answer

Strong Consistency

Question 47

A potential disadvantage of using a write-invalidate protocol for cache coherence is:

Accepted Answer

Increased bus traffic due to invalidations when multiple processors write to the same location

Answer

Implementation complexity

Answer

Lower performance compared to write-broadcast

Question 48

In a sequential consistency model, the order of operations for a processor reading and then writing to a shared memory location is:

Accepted Answer

Read operation must complete before the write operation becomes visible to other processors

Answer

Operations can occur in any order as long as cache coherence is maintained

Answer

Write operation can occur before the read operation is complete

Question 49

In a Symmetric Multiprocessing (SMP) system, which of the following statements is true regarding memory access?

Accepted Answer

All processors have equal access to the shared memory.

Answer

Each processor has its own private memory space, with no shared memory.

Answer

Only a designated master processor can access the shared memory.

Question 50

Which cache coherence protocol is known for its simplicity but can lead to the 'false sharing' problem?

Accepted Answer

Write-Invalidate Protocol

Answer

MESI Protocol

Answer

Directory-based Protocol

Answer

Snooping Protocol

Question 51

A memory consistency model defines the order in which:

Accepted Answer

Memory operations from multiple processors are observed

Answer

Data is transferred between the main memory and the caches

Answer

Cache lines are allocated to different processors

Question 52

Which memory consistency model provides the strongest ordering guarantees but may have performance implications?

Accepted Answer

Sequential Consistency

Answer

Total Store Order

Answer

Cache Coherence

Answer

Relaxed Consistency

Question 53

A program running on a multiprocessor system experiences a significant performance degradation due to multiple processors constantly updating the same cache line. This scenario is likely caused by:

Accepted Answer

False Sharing

Answer

Memory Consistency Issues

Answer

Excessive Context Switching

Answer

Cache Coherence Protocol Inefficiency

Question 54

In a directory-based cache coherence protocol, the directory maintains information about:

Accepted Answer

The cache state of each cache line across all processors.

Answer

The frequency of access to each cache line.

Answer

The memory address of each cache line.

Question 55

Which of the following is a key difference between a shared memory architecture and a message-passing architecture?

Accepted Answer

Shared memory architectures use a single address space for all processors, while message-passing architectures use separate address spaces.

Answer

Shared memory architectures are more suitable for parallel processing than message-passing architectures.

Question 56

The 'write-update' protocol in a cache coherence system is similar to the 'write-invalidate' protocol except for:

Accepted Answer

It updates the shared cache lines in other processors when a write occurs.

Answer

It invalidates the shared cache lines in other processors when a write occurs.

Answer

It requires a central directory to manage cache coherence.